Semiconductor device manufacturing typically includes alternately forming conductive layers (or conductive regions) and insulation layers, and electrically connecting upper and lower conductive layers that are otherwise electrically insulated by the insulation layers, using contacts that are formed in predetermined regions of the insulation layer.
For example, when manufacturing a semiconductor memory device, conductive regions between gate electrodes which include source and drain regions, can be electrically connected to a bit line or a storage node. To provide this feature after forming the gate electrode, an insulation layer is typically formed and then etched through a photolithographic etching process to form a contact window that exposes the drain region. Then, the contact window may be filled with conductive material to form what can be referred to as a “bit line” contact plug. The manufacturing process can also include forming a bit line that is electrically connected to the bit line contact plug, then depositing an insulation layer again, and etching the insulation layer to form a contact window that exposes the source region. Then, a storage node contact plug is formed. A storage node can be formed that is electrically contacted to the storage node contact plug.
However, the distance between adjacent elements in the semiconductor substrate (i.e., the gate electrodes) can be reduced or made more narrow as manufacturing procedures and/or processes accommodate increased density configurations. As a result, the aspect ratio of the contact window that extends through the insulation layer may increase, such that the contact window may not entirely penetrate the insulation layer during the photolithographic process. In addition, a gate electrode may be exposed during the contact window etching process, particularly if there is misalignment, thereby potentially causing electrical bridging between the gate electrode and the contact plugs.
Accordingly, self-aligned contact technologies have been used in order to decrease the aspect ratio of the contact window or hole and to inhibit or prevent the electrical bridge. The self-aligned contact technologies typically use a material property between two separate insulating layers to establish a different etch rate with respect to a predetermined etch gas. Briefly explained, one insulation layer (e.g., a silicon nitride layer) can be formed on a top and sidewalls of the gate electrode in order to protect the gate electrode. An interlayer insulation layer (e.g., a silicon oxide layer) having etch selectivity with respect to the one insulation layer can be used. Then, the photolithographic process can be performed to selectively etch the interlayer insulation layer, thereby forming a contact window that exposes conductive regions between the gate electrodes. After this step, conductive materials can be filled in the contact window to form self-aligned contact pads. According to these conventional self-aligned contact technologies, the gate electrode may be protected by the one insulation layer (such as the silicon nitride layer), so that even in the presence of misalignment, the gate electrodes, especially the top thereof, may not be exposed when the interlayer insulation layer (the silicon oxide layer) is etched.
In conventional self-aligned contact technologies, in order to increase the likelihood that the gate electrode is protected during fabrication, a silicon nitride capping layer can be formed on the top of the gate electrode and silicon nitride sidewall spacers can be formed on the sidewalls of the gate electrodes. Unfortunately, these spacers and the capping layer may cause problems, examples of which will be explained hereinafter.
For example, the silicon nitride capping layer typically increases a height of the stacked layer structure used to form the gate electrode(s). In addition, the space between neighboring gate electrodes may decrease due to the silicon nitride sidewall spacers. Therefore, during fabrication, the space between neighboring gate electrodes may not fill properly with the interlayer insulating layer, thereby potentially causing void and undesired electrical bridging in the subsequent process. Moreover, because the gate-stacked structure is relatively high, ion implantation may be difficult to perform. The conductive region (i.e., the source and drain regions), which is exposed by the self-aligned contact window, is typically limited in an area by the sidewall spacers. As a result, contact resistance between the source/drain region and self-aligned contact pad can increase. In addition, the gate electrode can be surrounded by the silicon nitride layer, such that loading capacitance may increase and the operation speed of the device may decrease.
Meanwhile, in the case of a transistor composing a logic circuit, a self-aligned silicide layer (i.e., salicide) may be used for high-speed operation. That is, refractory metal can be formed on top of the gate electrode and on the source/drain regions at both sides thereof. The refractory metal and silicon can then be thermally treated to form a silicide layer based on the reaction between the refractory metal and the silicon. When a logic circuit and a memory device are formed in the same chip for a high-speed operation and a highly integrated memory device, the conventional self-aligned contact techniques may cause several problems.
During operation, a top of the gate electrode of the memory device should be protected with an insulating layer, such as a silicon nitride layer, in order to use a conventional self-aligned contact method to form the memory device. However, in case of the logic device, the top of the gate should typically be exposed for forming the silicide layer. To compensate for the two disparate features, the fabrication process can become increasingly complicated. In addition, when forming the memory device, the silicide layer may be formed in order to secure a low resistance. However, the top of the gate may be protected by silicon nitride such that it may be difficult to form a silicide layer. In addition, when forming the logic device, the silicide layer can be formed in the source/drain regions, such that the gate sidewall spacers may be formed relatively thick to make the source/drain regions have an increased length. In other words, the length may depend on the width or thickness of the gate sidewall spacers. However, the sidewall spacers should be formed relatively thin at the cell region in order to inhibit generating voids.